Architecture-Aware Hierarchical Probabilistic Source Optimization

This paper focuses on architecture-aware source-level code transformation methods for low energy consumption in complex VLIW processors. Though energy issue has long been addressed at hardware level, but a significant contribution of software applications can not be ignored. Successive energy-cycle cost guarded parametric optimization are applied in proposed iterative compilation environment to evaluate an application expression profile on complex multimedia processors. The optimization is based on a multi objective function. The constraints of this objective function are formulated using a penalty method; a genetic algorithm finds solutions eventually. The proposed new code transformation methodology determines appropriate parameters for compiler optimization in order to satisfy user constraints on code size, energy, execution time and optimal target architecture usage. The set of experiments presented here characterize the newly introduced approach, while giving an idea about the architecture-based energy-cycle performance issues. Experimental results show that our approach reduces cache misses by an average of 33% (max. 67%), improves typically energy dissipation up to 23% and CPU performance up to 80% for an MPEGdec video algorithm. The approach is general and can easily be integrated in multimedia processor compilers.